module fetch1(
        input   [31:2]  i_pc, // cgen: source=pc_d

        // to next stage
        output          o_valid,
        output  [31:2]  o_pc,

        // pipeline control
        input           i_exec, // cgen: type=none cname=exec_pre_ex1

        // to cpu
        output  [31:2]  o_cpu_pc_q  // cgen: type=output cname=o_pc_q
);

assign o_valid = i_exec;
assign o_pc = i_pc;
assign o_cpu_pc_q = i_pc;

endmodule
